Title :
A double precision floating point multiply
Author :
Montoye, R. ; Belluomini, W. ; Ngo, H. ; McDowell, C. ; Sawada, J. ; Nguyen, T. ; Veraa, B. ; Wagoner, J. ; Lee, M.
Author_Institution :
IBM Austin Res. Lab., TX, USA
Abstract :
A 2.2GHz 53/spl times/54 bit pipelined multiplier is fabricated in 130nm CMOS technology with an area of 0.15mm/sup 2/. The circuit implementation results in a 50% size reduction over the previously reported values. The circuit operates at 2.2GHz and uses 522mW at 80% switching factor, 1.2V supply and 25/spl deg/C.
Keywords :
CMOS logic circuits; floating point arithmetic; multiplying circuits; pipeline arithmetic; 1.2 V; 130 nm; 2.2 GHz; 25 degC; 522 mW; CMOS; double precision floating point multiply; pipelined multiplier; size reduction; switching factor; CMOS logic circuits; CMOS technology; Clocks; Inverters; Latches; Logic circuits; Logic devices; Power dissipation; Switches; Switching circuits;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234323
