Title :
Scalable sub-10ps skew global clock distribution for a 90nm multi-GHz IA microprocessor
Author :
Bindal, N. ; Kelly, T. ; Velastegui, N. ; Wong, K.L.
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
A three-level clock distribution design for a next generation IA microprocessor is implemented in a 1.2V, 90nm process that scales to a 5GHz range. It achieves sub-10ps global clock uncertainty and addresses in-die variation, RLC delay matching, and scalability with die size and process issues without additional clock jitter or layout area. Risk management of practical constraints due to schedule, changing floor plan, loading and process are discussed.
Keywords :
clocks; delays; integrated circuit layout; microprocessor chips; 1.2 V; 5 GHz; 90 nm; RLC delay matching; die size; floor plan; global clock uncertainty; in-die variation; loading; multi-GHz IA microprocessor; risk management; scalability; skew global clock distribution; three-level clock distribution; Attenuation; Clocks; Delay; Energy consumption; Inverters; Jitter; Microprocessors; Phase locked loops; Resistors; Wires;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234329
