Title :
A digitally calibrated 5.15-5.825GHz transceiver for 802.11a wireless LANs in 0.18/spl mu/m CMOS
Author :
Bouras, J. ; Bouras, S. ; Georgantas, T. ; Haralabidis, N. ; Kamoulakos, G. ; Kapnistis, C. ; Kavadias, S. ; Kokolakis, Y. ; Merakos, P. ; Rudell, J. ; Plevridis, S. ; Vassiliou, I. ; Vavelidis, K. ; Yamanaka, A.
Author_Institution :
Athena Semicond., Athens, Greece
Abstract :
This transceiver achieves a transmit 1dB output compression point of +15dBm, and the overall receiver noise figure is 5dB. A power gain range of >45dB/65dB for transmit/receive and a PLL synthesizer frequency range of 4.9 to 5.85GHz with -79dBc/Hz phase noise at 10kHz offset have been measured. The IC is realized in 0.5/spl mu/m SiGe BICMOS technology and occupies 17mm/sup 2/.
Keywords :
BiCMOS integrated circuits; phase locked loops; phase noise; transceivers; wireless LAN; 0.18 micron; 0.5 micron; 4.9 to 5.85 GHz; 5 dB; 5.15 to 5.825 GHz; 802.11a wireless LANs; BiCMOS technology; CMOS; PLL synthesizer frequency range; output compression point; phase noise; power gain range; receiver noise figure; transceiver; BiCMOS integrated circuits; Frequency measurement; Frequency synthesizers; Gain measurement; Noise figure; Phase locked loops; Phase noise; Power measurement; Transceivers; Wireless LAN;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234331
