A 0.9 V 0.5 /spl mu/W CMOS single-switched-op-amp signal-conditioning system for pacemaker applications

Author

Cheung, V.S.L. ; Luong, H.C.

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

408

Abstract

A 0.5 /spl mu/W switched-capacitor signal-conditioning system with integrated switched-op-amp filter and /spl Sigma//spl Delta/ modulator is implemented in a 0.35 /spl mu/m CMOS process. A power-efficient single op-amp architecture employing half-delay SC integrators is utilized for the whole system. Operated from a 0.9 V supply, the system has a dynamic range of 45 dB.

Keywords

CMOS analogue integrated circuits; analogue processing circuits; integrating circuits; low-power electronics; medical signal processing; operational amplifiers; pacemakers; sigma-delta modulation; switched capacitor filters; /spl Sigma//spl Delta/ modulator; 0.35 micron; 0.5 muW; 0.9 V; CMOS single-switched-op-amp signal-conditioning system; dynamic range; half-delay SC integrators; integrated switched-op-amp filter; pacemaker applications; power-efficient single op-amp architecture; switched-capacitor signal-conditioning system; CMOS technology; Capacitors; Clocks; Energy consumption; Filters; Interference suppression; Operational amplifiers; Pacemakers; Stability; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234360

Filename

1234360