Title :
A 100 MHz DDS with synchronous oscillator-based phase interpolator
Author :
Badets, F. ; Belot, D.
Author_Institution :
STMicroelectronics, Crolles, France
Abstract :
A synchronous oscillator-based phase interpolator is used to lower spurious tones of a 100 MHz 16 b DDS. The synchronous oscillator locked-loop produces an eight-phase clock with coarse phase interpolation, while eight identical oscillators coupled with a DAC provide accurate phase adjustment. Spurious tone reduction obtained with the accurate phase interpolation is about 20 dB.
Keywords :
BiCMOS digital integrated circuits; Ge-Si alloys; digital-analogue conversion; direct digital synthesis; interpolation; phase locked loops; relaxation oscillators; 0.25 micron; 100 MHz; 100 MHz DDS; 16 bit; BiCMOS SiGe technology; DAC; SiGe; coarse phase interpolation; eight-phase clock; phase adjustment; spurious tone reduction; spurious tones; synchronous oscillator locked-loop; synchronous oscillator-based phase interpolator; Charge pumps; Circuits; Current supplies; Delay; Detectors; Filters; Frequency synchronization; Injection-locked oscillators; Linearity; Phase detection;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234361
