Fast waveform digitization with the DRS chip

The DRS chip was developed recently at PSI, Switzerland, using a 0.25 mum radiation hard CMOS technology. It implements a series of switched capacitor arrays (SCA), which allow the digitization of signals at speeds up to 5 GHz, at a power consumption and fabrication cost orders of magnitude lower than conventional flash ADCs. This allows a new generation of experiments with superior pile-up rejection and pulse shape discrimination, while simultaneously eliminating the need for traditional ADCs and TDCs. This paper explains the operating principle of the DRS chip and describes the deployment in the MEG experiment using 3000 channels in the MIDAS DAQ framework. Real time aspects of the data acquisition are covered and solutions are shown how to overcome the 880 MB/s raw data rate of the MEG experiment.