Title :
Instruction sets and their implementations
Author :
Flynn, Michael J.
Author_Institution :
EE Dept., Stanford Univ., CA, USA
Abstract :
A view of some of the major issues facing architects and designers in the nineties is presented. For example, as processor cycles shorten the number of cycles per instruction increases, since cache/memory access time does not scale with processor speed. Thus, the kind of tradeoffs applicable in the eighties may be quite different in the nineties
Keywords :
computer architecture; instruction sets; cache/memory access time; computer architecture; instruction sets; processor cycles; Bandwidth; Computer architecture; Costs; Instruction sets; Isolation technology; Microprocessors; Performance evaluation; Pins; Process design; Size measurement;
Conference_Titel :
Microprogramming and Microarchitecture. Micro 23. Proceedings of the 23rd Annual Workshop and Symposium., Workshop on
Conference_Location :
Orlando, FL
Print_ISBN :
0-8186-2124-9
DOI :
10.1109/MICRO.1990.151410
