Title :
A reduced-power algorithm and VLSI architecture for sequential decoding
Author :
Simmons, S.J. ; Tsui, S.
Author_Institution :
Queen´´s Univ., Kingston, Ont., Canada
Abstract :
A new algorithm and associated VLSI architecture for sequential decoding of convolutional codes is described. Its error rate performance is found to be virtually identical to that of the classical stack algorithm, while the expected power consumption of the described VLSI implementation is found to be at least one order of magnitude smaller (depending on channel bit error rate) than that of a previously proposed architecture, for nearly the same decoding speed
Keywords :
CMOS logic circuits; VLSI; convolutional codes; error statistics; sequential decoding; CMOS implementation; VLSI architecture; channel bit error rate; convolutional codes; decoding speed; error rate performance; parallel control logic; power consumption; reduced-power algorithm; sequential decoding; serial control logic; stack algorithm; Bit error rate; Convolutional codes; Energy consumption; Error analysis; Maximum likelihood decoding; Maximum likelihood detection; Solids; Termination of employment; Very large scale integration;
Conference_Titel :
Electrical and Computer Engineering, 2000 Canadian Conference on
Conference_Location :
Halifax, NS
Print_ISBN :
0-7803-5957-7
DOI :
10.1109/CCECE.2000.849668
