• DocumentCode
    2109721
  • Title

    Context-aware Post Routing Redundant Via Insertion

  • Author

    Chu, Po-Heng ; Lin, Rung-Bin ; Hsu, Da-Wei ; Chen, Yu-Hsing ; Tseng, Wei-Chih

  • Author_Institution
    Comput. Sci. & Eng., Yuan Ze Univ., Chungli
  • fYear
    2009
  • fDate
    13-15 May 2009
  • Firstpage
    37
  • Lastpage
    42
  • Abstract
    Effective algorithms have been invented for post-routing redundant via insertion (RVI). However, implementations of these algorithms often ignore some practical issues. In this article, we implement a post-routing RVI algorithm that takes into account interconnect contexts during RVI. Experimental results show that our context-aware RVI on average raises via1 (vias between metal layer 1 and 2) insertion rate from 37.4% to 72.1% and total insertion rate from 72.5% to 85.8%. On average, it increases RVI rate of critical paths by 3.6%. Besides, with redundant pin-area minimization, our approach reduces metal 1 and metal 2 area used for RVI at pins by 3%.
  • Keywords
    telecommunication network routing; ubiquitous computing; context aware; critical paths; post routing redundant via insertion; Circuit testing; Joining processes; Libraries; Logic gates; Minimization; Pins; Routing; Timing; Wire; Wiring; Redundant via; VLSI; design for manufacturing; double via;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 2009. ISVLSI '09. IEEE Computer Society Annual Symposium on
  • Conference_Location
    Tampa, FL
  • Print_ISBN
    978-1-4244-4408-3
  • Electronic_ISBN
    978-0-7695-3684-2
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2009.39
  • Filename
    5076380