Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs

Increasing on-chip power densities with aggressive technology scaling has led to a low-power FPGA fabric with dual supply voltages. Such low-power techniques coupled with the heterogeneity of components on a FPGA have led to non-uniform aging of components due to temperature and voltage dependent failure mechanisms. In this paper, we present techniques in placement and routing stages of the design flow that will increase the average life-time of components by ensuring uniform aging. We first study the impact of temperature and voltage variations on lifetime reliability of components. In the presence of such variations, we study the impact of aging in FPGA interconnects due to Electromigration (EM), and dielectric breakdown due to Time Dependent Dielectric Breakdown (TDDB). We also consider the performance degradation due to Hot Carrier Instability (HCI) in our design flow optimizations. The proposed reliability aware design flow techniques achieve an average of 65.8% and 75% improvement in lifetime of LUTs and interconnect wires respectively.