Ultra-low-power CMOS technologies

Author

Schrom, G. ; Selberherr, S.

Author_Institution

Inst. for Microelectron., Tech. Univ. Vienna, Austria

Volume

1

fYear

1996

fDate

9-12 Oct 1996

Firstpage

237

Abstract

The fast growing portable-electronics market as well as thermal dissipation, reliability, and scalability issues have launched a massive trend towards low-power and low-voltage technologies. This has lead to a new, reduced standard digital CMOS supply voltage of 3.3 V reducing the power consumption by 70%. However, the power consumption can still be cut down substantially by reducing the supply and threshold voltages much further without compromising systems performance. A loss in device speed can be compensated on the systems level by appropriate parallel architectures. Based on this concept of ultra-low-power CMOS technologies we explore the lower limits of CMOS supply voltage and switching energy for a variety of circuit classes analytically and numerically. Ultra-low-power (ULP) process and device design, device modeling, performance evaluation, and the specific problems associated with ULP mixed-analog-digital technologies are discussed

Keywords

CMOS integrated circuits; integrated circuit technology; mixed analogue-digital integrated circuits; 3.3 V; ULP mixed-analog-digital technology; low-voltage technology; parallel architecture; portable electronics; power consumption; reliability; scalability; supply voltage; switching energy; thermal dissipation; threshold voltage; ultra-low-power CMOS technology; CMOS technology; Circuit analysis; Energy consumption; Parallel architectures; Process design; Scalability; Semiconductor device modeling; Switching circuits; System performance; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference, 1996., International

Conference_Location

Sinaia

Print_ISBN

0-7803-3223-7

Type

conf

DOI

10.1109/SMICND.1996.557352

Filename

557352