Title :
Comparative Analysis of Timing Yield Improvement under Process Variations of Flip-Flops Circuits
Author :
Mostafa, Hassan ; Anis, M. ; Elmasry, M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON
Abstract :
In synchronous systems, any violation of the timing constraints of the flip-flops can cause the overall system to malfunction. Moreover, the process variations create a large variability in the flip-flop delay in scaled technologies impacting the timing yield. Overtime, many gate sizing algorithms have been introduced to improve the timing yield. This paper presents an analysis of timing yield improvement of four commonly used flip-flops under process variations. These flip-flops are designed using STMicroelectronics 65-nm CMOS technology. The analyzed flip-flops are compared for power and power-delay product (PDP) overheads to achieve this timing yield improvement. The analysis shows that the sense amplifier based flip flop (SA-FF) has a power overhead and PDP overhead of 1.7X and 2.8X, respectively, much higher than that of the transmission-gate master-slave flip flop(TG-MSFF) . The TG-MSFF exhibits the lowest relative power and PDP overheads of 30.87% and 9% ,respectively.
Keywords :
CMOS integrated circuits; flip-flops; timing circuits; CMOS technology; STMicroelectronics; flip-flop delay; flip-flops circuits; gate sizing algorithms; power overhead; power-delay product; process variations; sense amplifier; size 65 nm; timing yield improvement; transmission-gate master-slave flip flop; CMOS process; CMOS technology; Circuits; Clocks; Delay effects; Flip-flops; Master-slave; Sampling methods; Timing; Very large scale integration; Flip-flops; Process variations; Timing yield; statistical gate sizing;
Conference_Titel :
VLSI, 2009. ISVLSI '09. IEEE Computer Society Annual Symposium on
Conference_Location :
Tampa, FL
Print_ISBN :
978-1-4244-4408-3
Electronic_ISBN :
978-0-7695-3684-2
DOI :
10.1109/ISVLSI.2009.23
