A High-Speed GCD Chip: A Case Study in Asynchronous Design

This paper presents the design of a greatest common divisor (GCD) chip as a case study in asynchronous or clockless design. The design uses fine-grain asynchronous pipelining to achieve fairly high performance. At the same time, the use of robust asynchronous handshaking in lieu of clocking allows the design to gracefully adapt its operation to voltage and temperature variations, without the need for clock recalibration. The design was fabricated in a 0.13mum CMOS process, using standard cells and with full testability support. Resulting chips were evaluated for performance and robustness, using a large set of test vectors for good fault coverage. Under nominal operating conditions (1.5 V and 27degC), the fabricated parts were able to deliver up to 8 giga GCD algorithmic iterations per second (equivalent to 1 GHz clock speed). Moreover, they were functionally correct across a wide range of voltages (0.5 V to 4 V) and temperatures (-45degC to 150degC). This case study bolsters our confidence in the potential of aynchronous design techniques to help produce reliable ASICS that are fast, testable, and that operate under a wide range of conditions.