DocumentCode :
2110524
Title :
NoC Power Optimization Using a Reconfigurable Router
Author :
Concatto, Caroline ; Matos, Debora ; Carro, Luigi ; Kastensmidt, Fernanda ; Susin, Altamiro ; Kreutz, Marcio
Author_Institution :
PGMICRO, UFRGS - Fed. Univ. of Rio Grande do Sul, Porto Alegre
fYear :
2009
fDate :
13-15 May 2009
Firstpage :
235
Lastpage :
240
Abstract :
In real applications there are different communication needs among the cores. When NoCs are the means to interconnect the cores, the use of some techniques to optimize the communication are indispensable. From the performance point of view, large buffer sizes ensure performance during different applications execution, but unfortunately, these same buffers are the main responsible for the router total power dissipation. Another aspect is that by sizing buffers for the worst case latency incurs in extra dissipation for the mean case, which is much more frequent. To cope with this problem, in this paper we propose a dynamically reconfigurable router for a NoC. With the reconfigurable router it was possible to reduce the congestion in the network, while at the same time reducing power dissipation and improving energy.
Keywords :
integrated circuit interconnections; network routing; network-on-chip; optimisation; reconfigurable architectures; NoC power optimization; core interconnect; network congestion; network-on-chip; power dissipation; reconfigurable router; Bandwidth; Computer Society; Costs; Delay; Network-on-a-chip; Parallel processing; Power dissipation; Power system interconnection; Scalability; Switches; FIFO; Network-on-Chip; latency; power dissipation; reconfigurable router;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 2009. ISVLSI '09. IEEE Computer Society Annual Symposium on
Conference_Location :
Tampa, FL
Print_ISBN :
978-1-4244-4408-3
Electronic_ISBN :
978-0-7695-3684-2
Type :
conf
DOI :
10.1109/ISVLSI.2009.7
Filename :
5076413
Link To Document :
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