DocumentCode
2110918
Title
Gate-level fault diagnosis for scan-based VLSI environment
Author
Xu, Y.W. ; Sun, X.
Author_Institution
Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada
Volume
1
fYear
2000
fDate
2000
Firstpage
390
Abstract
This paper presents a gate-level fault diagnostic scheme for integrated circuits with STUMPS based built-in self-test (Bardell and McAnney 1982). It first employs a structural analysis algorithm to eliminate modeled faults that do not produce observed erroneous circuit outputs, then uses a dynamic fault dictionary and signature simulation technique to improve on the fault diagnostic resolution
Keywords
VLSI; built-in self test; fault simulation; integrated circuit testing; STUMPS based built-in self-test; circuit outputs; dynamic fault dictionary; gate-level fault diagnosis; integrated circuits; scan-based VLSI environment; signature simulation technique; structural analysis algorithm; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Dictionaries; Failure analysis; Fault diagnosis; Flip-flops; Logic testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Computer Engineering, 2000 Canadian Conference on
Conference_Location
Halifax, NS
ISSN
0840-7789
Print_ISBN
0-7803-5957-7
Type
conf
DOI
10.1109/CCECE.2000.849736
Filename
849736
Link To Document