Analysis of temperature effects on maximum power-efficiency of pass transistor logic networks in low-voltage CMOS

Author

Allam, A. ; Khanafshar, O. ; Kwok, D. ; Rysinski, J. ; Wang, H. ; Wickman, C. ; Margala, M.

Author_Institution

Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada

Volume

1

fYear

2000

fDate

2000

Firstpage

399

Abstract

This paper presents a comprehensive analysis of the effects of increased temperature on maximum power-efficiency (powerd-delay-product) of pass-transistor networks operating at low supply voltages using deep-submicron CMOS technology. Numerous gate functions, such as OR, NOR, AND, NAND, XOR and XNOR have been designed in double pass-transistor logic (DPL) and swing-restored pass-transistor logic (SRPL). These circuits have been investigated under various operating conditions: fanin, fanout, power supply voltage and temperature. The results show that increased temperature significantly affects the maximum power-efficiency operating point of these logic gates and consequently, the optimum operating point

Keywords

CMOS logic circuits; integrated circuit design; logic design; logic gates; double pass-transistor logic; fanin; fanout; gate functions; logic gates; low-voltage CMOS; maximum power-efficiency; maximum power-efficiency operating point; optimum operating point; pass transistor logic networks; power supply voltage; powerd-delay-product; swing-restored pass-transistor logic; temperature effects; CMOS logic circuits; CMOS technology; Energy consumption; Intelligent networks; Logic design; Logic devices; Logic gates; Page description languages; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2000 Canadian Conference on

Conference_Location

Halifax, NS

ISSN

0840-7789

Print_ISBN

0-7803-5957-7

Type

conf

DOI

10.1109/CCECE.2000.849738

Filename

849738