A new circuit topology for LNAs using partial source degeneration with double transistor connection to improve gain and input impedance matching flexibility

One of the most important constraints that a designer must face in LNA design is the input impedance matching. The input impedance matching results in optimized gain and noise figure for the amplifier. Considering a single MOS transistor in common-source configuration, a degeneration of the source by an inductance Ls produces a desirable real part on the input impedance. Unfortunately, due to some technology restrains the designer must work with restringed options for Ls values limiting the capability to achieve a desirable impedance. The degeneration also introduces transconductance reduction due to the Ls voltage drop.