Sigma-Delta fractional — N phase locked loop synthesizer for local positioning systems

The system design and implementation of Sigma-Delta modulator of fractional-N phase locked loop in local positioning systems are presented. The behavioral model of the complete SigmaDelta-fractional-N PLL was developed that provides phase noise and RMS phase jitter estimation and optimization as function of the unity gain frequency. It is shown that the level of RMS phase jitter obtained with a 3^rd order SigmaDelta fractional - N PLL is comparable to the levels of RMS phase jitter obtained with DDS realizations. However, SigmaDelta fractional-N PLL synthesizers present lower power consumption, compact design and better frequency ramp linearity than DDS realizations for linear FM systems. Digital and analog co-simulations and implementation of SigmaDelta-modulator and pre-emphasis IIR filter design were carried out. The measurement results of the SigmaDelta-modulator using a linear FM sweep were verified on Xilinix-FPGA platform.