DocumentCode :
2111633
Title :
Efficient implementation of log10 lookup table in FPGA
Author :
Seidner, D.
Author_Institution :
Dept. of Comput. Sci., Coll. of Manage., Rishon-Lezion
fYear :
2008
fDate :
13-14 May 2008
Firstpage :
1
Lastpage :
9
Abstract :
When implementing a mathematical function in h/w, we would like to minimize the required resources. This task is critical in FPGA designs. One of the popular techniques for implementing mathematical functions in h/w, is a lookup table (LUT) based design. In order to reduce the required memory size, the common implementations use a linear or 2nd order interpolation between a pre-defined set of input values for which the function values are stored in a LUT. In this paper we design an efficient FPGA implementation of a log10 conversion circuit. When trying to build such a circuit based on the conventional approach without scaling, one finds that the resulting error is unacceptable. We here suggest a simple ldquoautomatic scalingrdquo approach based on the mathematical properties of the log function that allows an efficient implementation. We then demonstrate the implementation of this approach in an FPGA.
Keywords :
digital arithmetic; field programmable gate arrays; interpolation; logic design; table lookup; FPGA design; field programmable gate arrays; linear interpolation; log function; log10 conversion circuit; log10 lookup table; mathematical function; Chebyshev approximation; Circuits; Computer science; Digital images; Educational institutions; Field programmable gate arrays; Image processing; Interpolation; Resource management; Table lookup;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microwaves, Communications, Antennas and Electronic Systems, 2008. COMCAS 2008. IEEE International Conference on
Conference_Location :
Tel-Aviv
Print_ISBN :
978-1-4244-2097-1
Electronic_ISBN :
978-1-4244-2098-8
Type :
conf
DOI :
10.1109/COMCAS.2008.4562810
Filename :
4562810
Link To Document :
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