DocumentCode :
2111637
Title :
The Heterogeneous Architecture of Multi-Core Research and Design
Author :
Li, Jing Mei ; Jiao, Ping ; Men, Chao Guang
Author_Institution :
Harbin Eng. Univ., Harbin, China
fYear :
2009
fDate :
20-22 Sept. 2009
Firstpage :
1
Lastpage :
6
Abstract :
Aiming at the problem that it was difficult to improve the processor performance only by improve the frequency of the clock, as well as superscalar pipeline stall, the paper introduced an architecture of heterogeneous Multi-Core processor which used the Loop Detector, special Queuing Backup Ins Queue, C-Core processor controller, and C-Bus which among of E-Core. The architecture not only optimized loop program, and avoided the pipeline flushed due to branch miss-predict. So the architecture could improve overall efficiency of Multi-Core processor.
Keywords :
microprocessor chips; queueing theory; C-Bus; C-Core processor controller; E-Core; heterogeneous multicore processor; loop detector; loop program; multicore design; multicore research; queuing backup ins queue; Chaos; Clocks; Computer architecture; Design engineering; Detectors; Frequency; Manufacturing processes; Multicore processing; Parallel processing; Pipelines;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Management and Service Science, 2009. MASS '09. International Conference on
Conference_Location :
Wuhan
Print_ISBN :
978-1-4244-4638-4
Electronic_ISBN :
978-1-4244-4639-1
Type :
conf
DOI :
10.1109/ICMSS.2009.5302477
Filename :
5302477
Link To Document :
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