• DocumentCode
    2112566
  • Title

    An Optimized Architecture Implementing the Standard JPEG Algorithm on FPGA

  • Author

    Quazi, Habeebuddin ; Qader, Fayzan ; Rasheed, Muhammad Junaid ; Mansoor, Hasnain

  • Author_Institution
    NED Univ. of Eng. & Technol., Karachi
  • fYear
    2005
  • fDate
    27-27 Aug. 2005
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    The JPEG algorithm is one of the best compression algorithms. It preserves a good quality while reducing the size to a large extent. It uses advanced image analysis techniques to reduce size while losing the lesser important information. This paper describes a simple and efficient architecture to implement a JPEG encoder trying to use as less resources as possible without compromising much speed or quality.
  • Keywords
    data compression; field programmable gate arrays; image coding; FPGA; JPEG encoder; compression algorithms; image analysis techniques; Computer architecture; Control systems; Discrete cosine transforms; Encoding; Entropy; Field programmable gate arrays; Image coding; Quantization; Telecommunication control; Transform coding; Entropy; FPGA; JPEG; Verilog; baseline;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Engineering Sciences and Technology, 2005. SCONEST 2005. Student Conference on
  • Conference_Location
    Karachi
  • Print_ISBN
    978-0-7803-9442-1
  • Electronic_ISBN
    978-0-7803-9442-1
  • Type

    conf

  • DOI
    10.1109/SCONEST.2005.4382888
  • Filename
    4382888
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2112566