A Stacked NoC Architecture for Quality-of-Service

As CMOS technology enters sub-micron era, a large number of intelligent properties (IPs) are integrated on a single chip (SoC). The communication patterns become difficult to model. At the same time, as transistors become small and wires become narrow, delays are becoming more and more unpredictable. The factors greatly challenge traditional on-chip buses and point-to-point interconnects because of their problems of scalability and flexibility. In the paper, we propose a stacked on-chip network architecture to provide reliable and efficient on-chip communication in SoCs. The architecture uses a delay-insensitive asynchronous physical channel control scheme and reserved virtual channel control scheme to guarantee the quality-of-service of the on-chip network.