Novel CMOS static ternary logic using double pass-transistor logic

A new static ternary double pass-transistor logic (TDPL) has been developed with some favourable properties: perfectly symmetrical structure, full logic swing and the maximum possible noise margins, the use of the standard CMOS process without any modification of the thresholds, the less complex structure, and no static power consumption. The proposed scheme consists of complementary inputs/outputs and is thus a dual rail ternary logic. HSPICE simulations using 0.3µm CMOS technology and a 3V power supply demonstrate the effectiveness of the proposed design approach.