Design and implementation of a programmable stack filter

Proposes two simple and efficient architectures for the realization of stack filters in hardware: one for pipelined implementation and the other for non-pipelined implementation. Both architectures are interchangeable, with very minor modifications. A programmable stack filter has been layed out based on the proposed pipelined architecture in the AMS 1 micron technology using Mentor Graphics Generator Design Tools for five words of twelve bits each and simulations have been carried out successfully using the Mentor Graphics Lsim simulator. Results are encouraging that the simulations are error-free at a frequency as high as 166 MHz