Title :
Self-shielded high voltage SOI structures for HVICs
Author :
Nolhier, Nicolas ; Charitat, G. ; Zerrouk, D. ; Rossel, P.
Author_Institution :
Lab. d´´Anal. et d´´Archit. des Syst., CNRS, Toulouse, France
Abstract :
We report in this paper a numerical study on an electrical isolation scheme for High Voltage Integrated Circuits (HVICs). The presented architecture is based on mixed-isolation technique including a vertical dielectric isolation along with an horizontal junction isolation. The aim of this work is the integration on the same substrate of power devices with low voltage control circuits. This isolation technique must be efficient in both static and dynamic mode, in order to compete with a costly full dielectric isolation
Keywords :
isolation technology; power integrated circuits; shielding; silicon-on-insulator; HVIC; dynamic mode; electrical isolation; high voltage integrated circuit; horizontal junction isolation; low voltage control circuit; mixed isolation; power device; self-shielded SOI structure; static mode; vertical dielectric isolation; Breakdown voltage; Capacitors; Computer architecture; Costs; Isolation technology; Low voltage; MOSFETs; Numerical simulation; Shape; Silicon;
Conference_Titel :
Semiconductor Conference, 1996., International
Conference_Location :
Sinaia
Print_ISBN :
0-7803-3223-7
DOI :
10.1109/SMICND.1996.557368
