Title :
The SPH-graph: a model to support VLSI design
Author :
Ancona, M. ; Clematis, A. ; De Floriani, Leila ; Puppo, E.
Author_Institution :
Dept. of Math., Genoa Univ., Italy
Abstract :
A hierarchical graph-based model, called a structured hypergraph with ports (SPH-graph), is presented, that provides a structural description of VLSI objects at different levels of abstraction. The relationship between hardware description languages and the SPH-graph model are investigated by considering the VHSIC hardware description language (VHDL). It is shown, through an example, how a structural VHDL description of a hardware entity can be mapped on the model by using a basic set of primitives for SPH-graph manipulation.<>
Keywords :
VLSI; circuit CAD; graph theory; integrated circuit technology; logic CAD; specification languages; CAD; SPH-graph; VHDL; VHSIC hardware description language; VLSI design; computer aided design; hierarchical graph-based model; structural description; structured hypergraph; Circuit simulation; Computational modeling; Data structures; Design automation; Design methodology; Encoding; Hardware design languages; Integrated circuit interconnections; Very high speed integrated circuits; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo, Finland
DOI :
10.1109/ISCAS.1988.15143
