Impact of Pitch Reduction over Residual Strain of Flip Chip Solder Bump after Reflow

For heterogeneous materials assemblies, the thermal expansion mismatch between chip and substrate represents the most important bottleneck for ultra-fine pitch flip-chip bonding. Generally numerical stress analysis of flip chip ball grid array (BGA) package assemblies focus on the reliability of solders interconnects during thermal cycling. Here the purpose of our finite element modelling is to evaluate the degradations occurring during the flip chip process itself. Indeed, during the cool down to room temperature after reflow, the bumps are not mechanically protected by an underfill and the residual strain could become critical for fine pitch and large devices. We conduct a series of transient analysis with different geometrical configurations. As the most important difficulty to model fine pitch solder bump behavior is the increasing calculation time, a method to reduce the number of element was proposed. The maximal strain intensity of solder bumps were calculated for different pitches and die length, in order to evaluate the thermo-mechanical limits of soldering method