High level performance estimation for a primitive operator filter FPGA

The increase in complexity of current VLSI-based FPGA arrays has lead to a demand for efficient methods of estimating their performance characteristics at a higher level. This paper describes a technique for speed and area estimation of DSP-based FPGAs, using the example of a primitive operator filter FPGA, which targets the realisation of reduced complexity digital filters. The technique utilises information about the FPGAs; the constituent elements of its configurable blocks, in our case, adders, shifters, multiplexers and the CMOS technology under consideration. The paper describes the POF FPGA structure, and the development of metrics for speed and area performance estimation. Results are presented which show the efficiency of the estimation technique