Research on Eliminating Common-mode Voltage of Cascaded High-voltage Inverter Based on SVM

To eliminate common-mode voltage (CMV) of cascaded multi-level inverter, a novel strategy is carried out respectively in the point of 2-level SVM and 3-level SVM, which can be easily applied in cascaded high voltage (HV) inverters by sampling time staggered technique. The concept of left-and-right leg groups is proposed for the special structure of 2-level SVM, and the phase difference between two reference vectors is set to be 2¿/3 to suppress the CMV. On 3-level SVM mode, as each one cascade can generate three levels, only zero-CMV vectors are selected for modulation in order to decrease the CMV. Applying the above two SVM strategies to cascaded HV inverters by sampling time staggered (STS) technique, the CMV can be completely eliminated theoretically. Experimental results testified the effectiveness of the above two methods.