Title :
An instruction reorderer for pipelined computers
Author :
Shieh, Jong-Jiann ; Papachristou, Christos A.
Author_Institution :
Dept. of Inf. Eng., Tatung Inst. of Technol., Taipei, Taiwan
Abstract :
The authors proposed an algorithm previously (1989) to reorder the straight line instruction streams for pipelined computers. In this paper, they extend the algorithm to handle streams with branches and loops as well. The input is the intermediate code of a compiler and is represented by the data control dependence graph (DCG). The DCG is preprocessed to construct a branch nest tree which is related to the structure of the branches and loops within the instruction streams. A priority list is then constructed for scheduling the nodes. The algorithm finds a most suitable slot for each node of the DCG
Keywords :
instruction sets; pipeline processing; branch nest tree; branches; compiler; data control dependence graph; instruction reorderer; loops; pipelined computers; priority list; straight line instruction streams; streams; Art; Clocks; Computer aided instruction; Computer architecture; Hazards; Pipelines; Processor scheduling; Registers; Throughput; Tree graphs;
Conference_Titel :
Microprogramming and Microarchitecture. Micro 23. Proceedings of the 23rd Annual Workshop and Symposium., Workshop on
Conference_Location :
Orlando, FL
Print_ISBN :
0-8186-2124-9
DOI :
10.1109/MICRO.1990.151435
