Design of link layer controller for high speed serial bus

This paper designs a link layer controller for a serial bus that based on the IEEE 1394 standard. The design is compatible with the interface of physical-layer chips, and able to work at up to 400Mbps in asynchronous transmission mode. Fig. 1 shows the structure of the controller. Based on the analysis of the function of PHY-interface, Fig. 3 shows the control FSM of the PHY-interface. A speed auto-adaptive and no latency CRC, which could improve the transmission reliability, is proposed and it is implemented as shown in Fig. 4. The communication protocol between the link layer controller and the host CPU is also defined. Finally the link-layer controller is described in verilog HDL, and implemented on FPGA. The experimental results show preliminarily that the controller we designed works well in an asynchronous high speed data transform network systems.