Title :
A CMOS frequency synthesizer with selfbiasing current source for a 5-GHz wireless LAN receiver
Author :
Quemada, C. ; Mendizabal, J. ; Presa, J. ; Adin, I. ; Legarda, J. ; Bistue, G.
Author_Institution :
Centra de Estudios e Investigaciones Tecnicas de Gipuzkoa, San Sebastian, Spain
Abstract :
In this work, an integrated 3.2 GHz phase locked loop (PLL) with a selfbiasing current source is presented. The circuit has been designed using a 3.3 V 0.18μm CMOS technology. The synthesizer consumes 55 mW of which 20 mW is consumed by the VCO. The PLL has a bandwidth of 100 KHz and a phase noise of -111 dBc/Hz at 1 MHz offset frequency. The spurious sidebands at the center of adjacent channels are less than -70 dBc. These results made the circuit suitable inside a 5 GHz wireless LAN receiver.
Keywords :
CMOS digital integrated circuits; frequency synthesizers; phase locked loops; superheterodyne receivers; voltage-controlled oscillators; wireless LAN; 1 MHz; 20 mW; 3.3 V; 5 GHz; 55 mW; CMOS technology; PLL; VCO; frequency synthesizer; phase locked loop; selfbiasing current source; voltage-controlled oscillators; wireless LAN receiver; wireless local area networks; Bandwidth; CMOS technology; Charge pumps; Circuits; Filters; Frequency conversion; Frequency synthesizers; Phase locked loops; Voltage-controlled oscillators; Wireless LAN;
Conference_Titel :
Personal, Indoor and Mobile Radio Communications, 2004. PIMRC 2004. 15th IEEE International Symposium on
Print_ISBN :
0-7803-8523-3
DOI :
10.1109/PIMRC.2004.1368326
