Title :
On graph representation of incomplete VLSI circuits
Author_Institution :
Silvar-Lisco, Menlo Park, CA, USA
Abstract :
The author presents a way to generate a complete graph for an incomplete circuit. Standard verification systems may then be used to check the incomplete design in a top-down environment. A similar approach may be used in a bottom-up design for the sake of saving CPU time. When going up the hierarchy, it is almost always more efficient to model the pins of the blocks instead of their contents. Once the contents of the block are verified, only the pins are included in the graph (modeled by resistors)
Keywords :
VLSI; circuit layout CAD; graph theory; CAD; bottom-up design; computer aided design; graph representation; incomplete VLSI circuits; top-down environment; Central Processing Unit; Circuit synthesis; Circuit topology; Error correction; Integrated circuit interconnections; Inverters; Process design; Resistors; Silicon; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo
DOI :
10.1109/ISCAS.1988.15144
