The selection of optimal cache lines for microprocessor-based controllers

The paper presents a method of selecting optimal line sizes of cache memories for microprocessor-based controllers. It is well known that the use of cache memories in microprocessor systems can greatly improve their performance, especially in a heavy-traffic environment. The authors analyze cache performance using trace-driven simulation, a widely used method that is considered to be effective in exploring cache hit ratios. Three cache parameters, cache sizes, set associativity and line sizes, which can directly impact the hit ratios, are investigated. Among the three parameters, they mainly focus on exploring the effects of selecting line sizes on the entire microprocessor performance. A significant observation is that, although increasing line sizes can result in a higher hit ratio, it also considerably increases traffic to main memory, thereby degrading the performance. This indicates that a larger line size with a slightly higher hit ratio may perform worse than a smaller one with a lower hit ratio. They therefore present a simple method of determining an optimal line size that produces the best overall system performance