Address compression through base register caching

The paper presents a technique to reduce processor-to-memory address bandwidth by exploiting temporal and spatial locality in address reference streams. Higher order portions of address words are cached in base registers at both the processor and memory. This makes it possible to transmit small register indexes between processor and memory instead of the high order address bits themselves. Trace driven simulations indicate that base register caching reduces processor-to-memory address bandwidth up to 60% without appreciable loss in performance