Title :
On the testing of microprogrammed processor
Author :
Hwang, S. ; Rajsuman, R. ; Malaiya, Y.K.
Author_Institution :
Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
Abstract :
A testing procedure is given for a microprogrammed processor. The conventional procedure to generate test vectors is used instead of C-testability for the bit-slice microprocessor. The minimal complete test sequences are calculated for the micro-sequencer and the ALU, and stored in the micro-memory. Micro-memory is implemented by an electrically erasable PLA which has the capability to test itself using a universal test set. A one-bit wide processor section is assumed. However, the method can be extended to a processor of any word length. The tests for the microsequencer and the ALU are applied from the micromemory. The response is compared against precalculated signature stored in the system memory. A parity bit is generated to indicate a fault
Keywords :
logic testing; microprocessor chips; microprogramming; ALU; C-testability; bit-slice microprocessor; electrically erasable PLA; micro-memory; micro-sequencer; microprogrammed processor; minimal complete test sequences; one-bit wide processor; parity bit; system memory; testing procedure; word length; Automata; Circuit faults; Circuit testing; Computer science; Logic arrays; Logic testing; Microprocessors; Programmable logic arrays; Sequential circuits; Very large scale integration;
Conference_Titel :
Microprogramming and Microarchitecture. Micro 23. Proceedings of the 23rd Annual Workshop and Symposium., Workshop on
Conference_Location :
Orlando, FL
Print_ISBN :
0-8186-2124-9
DOI :
10.1109/MICRO.1990.151452