An estimation of saturation current influenced by source and drain resistances for sub-20nm MOSFETs

In this work, we investigate the influence of source and drain resistances to saturation currents for sub-20nm MOSFETs. New device structures such as Multi-gate and FinFET have been researched in sub-20nm regime. In design of the structures, it is necessary to consider the influence of source and drain resistances. In the ITRS report, saturation current has been estimated by using an analytical program: MASTAR. Therefore, it is necessary to evaluate an accuracy of MASTAR. The saturation currents calculated by MASTAR are compared with results of circuit simulations considering the source and drain resistances. The difference between MASTAR and circuit simulations increases from 4.23% to 5.97% as the gate lengths are scaled down to 18 nm. Our results indicate that MASTAR overestimates the reduction of drain saturation currents due to the source and drain resistances.