A Kind VLSI Design of Vector Quantization Algorithm for Image Compression

The VLSI architecture is simulated and verified on a FPGA device successfully. The design is described at RTL level using Verilog HDL. Based on Altera Cyclone device EP1C12Q240C8, synthesis and post-simulation are conducted with Quartus II 4.2 and Modelsim SE Plus 5.8b. For the synthesized device 38% of the logic resource and 20% of the memory is used. The maximum clock frequency is 100.52 MHz. A new fast search algorithm for VQ which is appropriate for hardware implementation is proposed in this paper. In the new search algorithm, the codebook and the input image vectors are classified into three groups: horizontal (H), vertical (V) and even (E). The algorithm is simulated functionally and verified on FPGA. Verification result indicates that the new searching algorithm is more effective for hardware implementation and has higher speed. When the frequency is 50 MHz, the device can compress a 512times512 grayscale still image in 10 ms. The compression ratio is 16:1 and the quality of the reconstructed image is high. Furthermore, with some modification the encoding system can easily handle real-time video even color images.