The Realization of the 1GHz Negative Logarithmic Function Based on the 0.35um AMS Technology

Author

Ruan, Weihua

Author_Institution

Dept. of Electr. & Electron. Eng., Nanjing Inst. of Ind. Technol., Nanjing, China

fYear

2010

fDate

24-26 Dec. 2010

Firstpage

15

Lastpage

18

Abstract

This paper presents the realization of the 1GHz Negative Logarithmic Function (NLF) based on the 0.35um AMS technology. Firstly, it shows some interesting advance beyond Mitchell´s approach with hardware implementation of a sequential architecture minimized in terms of gates and thus optimized for power and area sensitive application. Secondly, it introduces the realization of the NLF using combinational logic only. Lastly, it presents the realization of the physical layout using the second method based on 0.35um AMS technology with Silicon Ensemble software.

Keywords

combinational circuits; sequential circuits; AMS technology; NLF; combinational logic; frequency 1 GHz; hardware implementation; negative logarithmic function; sequential architecture; sequential circuit; silicon ensemble software; size 0.35 mum; Computer architecture; Delay; Hardware; Microprocessors; Sequential circuits; Simulation; Software; Antilogarithm Function; LNS (Logarithmic Number System); Logarithmic Function; NLF (Negative Logarithmic Function); SCU (Score Calculating Unit);

fLanguage

English

Publisher

ieee

Conference_Titel

Information Science and Engineering (ISISE), 2010 International Symposium on

Conference_Location

Shanghai

ISSN

2160-1283

Print_ISBN

978-1-61284-428-2

Type

conf

DOI

10.1109/ISISE.2010.111

Filename

5945041