A Technology Based Benefit Analysis on Reuse of Vector Register for SIMD Vectorization Optimization

The reuse-rate of vector register is one of the most important aspects that influence the SIMD performance. However, the reuse of vector register probably can lead ton on-continuous memory access and non-hit of cache. Based on register reuse analysis, we establish a cost analysis that guide the multiple code generation. Then we perform NPB test based on different problem-scale and the result shows that program can reap an optimal performance as a result of this optimization, which can avoid low cache hit rate arose by vector register reuse for SIMD code generation.