A real-time multi-view interlacing architecture for auto-stereoscopic 3DTV display based on FPGA

In this paper, a multi-view interlacing hardware architecture for High-definition (HD) (1920×1080) auto-stereoscopic 3DTV display system on a Virtex-4 FPGA is presented. Our approach focuses on the image reconstruction after DIBR, which consists of pixel rearrangement, color space conversion between RGB and YCbCr and pixel downsampling for BT.1120 HDMI format output. The FPGA hardware architecture and the implementation algorithm are based on a proved software system, but improved a lot to achieve the realtime display effect. The experiment performances represent a sound result and can be improved to adapt to future SoC design and more complex 3DTV end to end system.