Review on Process-Induced Strain Techniques for Advanced Logic Technologies

We have extensively studied stress enhancing techniques to increase channel mobility starting at the 130 nm technology node and continued this towards the 45 nm node. Stressed overlayers and spacer materials, strained SOI substrates, embedded SiGe and SiC layers and their proximity effects, the impact of different silicides, stress memorization and compatibility with laser and flash anneals have been investigated. The integration of abovementioned techniques into a CMOS flow resulted in an outstanding pMOS and nMOS performance improvement, no reliability issues and no impact on short channel behavior.