Review on Process-Induced Strain Techniques for Advanced Logic Technologies

Author

Wiatr, M. ; Feudel, Th. ; Wei, A. ; Mowry, A. ; Boschke, R. ; Javorka, P. ; Gehring, A. ; Kammler, T. ; Lenski, M. ; Frohberg, K. ; Richter, R. ; Horstmann, M. ; Greenlaw, D.

Author_Institution

AMD Saxony LLC & Co. KG, Dresden

fYear

2007

fDate

2-5 Oct. 2007

Firstpage

19

Lastpage

29

Abstract

We have extensively studied stress enhancing techniques to increase channel mobility starting at the 130 nm technology node and continued this towards the 45 nm node. Stressed overlayers and spacer materials, strained SOI substrates, embedded SiGe and SiC layers and their proximity effects, the impact of different silicides, stress memorization and compatibility with laser and flash anneals have been investigated. The integration of abovementioned techniques into a CMOS flow resulted in an outstanding pMOS and nMOS performance improvement, no reliability issues and no impact on short channel behavior.

Keywords

CMOS logic circuits; annealing; CMOS flow; advanced logic technologies; channel mobility; flash anneals; laser anneals; nMOS; pMOS; process-induced strain techniques; proximity effects; spacer materials; stress memorization; Capacitive sensors; Germanium silicon alloys; Logic; Optical materials; Proximity effect; Silicides; Silicon carbide; Silicon germanium; Space technology; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Thermal Processing of Semiconductors, 2007. RTP 2007. 15th International Conference on

Conference_Location

Catania, Sicily

Print_ISBN

978-1-4244-1227-3

Electronic_ISBN

978-1-4244-1228-0

Type

conf

DOI

10.1109/RTP.2007.4383814

Filename

4383814