Limitations and challenges of multi-gigabit DRAM circuits

Author

Itoh, K. ; Nakagome, Y. ; Kimura, S. ; Watanabe, T.

Author_Institution

Central Res. Labs., Hitachi Ltd., Tokyo, Japan

fYear

1996

fDate

13-15 June 1996

Firstpage

2

Lastpage

7

Abstract

Limitations and challenges concerning multi-gigabit DRAM circuits were discussed in terms of high-density devices, high-performance circuits, and low-power/low-voltage circuits. There are many challenges related to MOSFET performance degradation, ever-lower cell-capacitance and stored voltage, increasingly complicated designs for high-speed chips, and increasing subthreshold-currents. Genuine breakthroughs are needed to overcome these challenges, and combined with the creation of new markets for multi-gigabit DRAMs, these anticipated breakthroughs will make the semiconductor industry more prosperous through the 21st century.

Keywords

DRAM chips; VLSI; cellular arrays; integrated circuit design; MOSFET performance degradation; cell capacitance; high-density devices; high-speed chips; low-power circuits; low-voltage circuits; multi-gigabit DRAM circuits; semiconductor industry; stored voltage; subthreshold-currents; Degradation; Electronics industry; MOSFET circuits; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-3339-X

Type

conf

DOI

10.1109/VLSIC.1996.507695

Filename

507695