Design of a 169% locking-range frequency divider with programmable input sensitivity

A wide locking-range frequency divider with programmable input sensitivity is presented in this paper. The frequency divider consists of two D flip-flop-based current mode logic latches and a current control circuit. The current control circuit adjusts the current ratio of the sampling pair and the latching pair, while the total current is maintained as a constant. The current control circuit enables the self-oscillation frequency to be adapted to the input frequency. As a result, the divider has wide locking range below -10 dBm input level. The proposed frequency divider is implemented in 0.18 um standard CMOS technology, and the measurement results show a 169% frequency locking range of between 0.5 and 6 GHz at an input power of - 10 dBm while consuming 7.2 mW from a 1.8 V supply voltage.