Title :
Performance modelling of a multiprocessor bus architecture
Author :
Hajare, Ankur R.
Author_Institution :
NASA Inf. Syst. Dept., Mitre Corp., Houston, TX, USA
Abstract :
This paper describes a discrete event simulation model of the bus architecture of a tightly coupled multiprocessor system. The newly announced multiprocessor system was being evaluated as a replacement for four old minicomputers with shared memory. The multiprocessor system was not yet available for benchmarking. Therefore, the models described here, along with other models, were used to estimate the performance of the multiprocessor system based on workload characterization of the old minicomputers that were being replaced. Two tools were used to build the simulation models. The performance models were first developed using the Performance Analysts Workbench System (PAWS). The second modelling tool, Network II.5, was subsequently used to model the same computer system as a part of an evaluation of that tool. A comparison of the models demonstrated the differences between the two tools
Keywords :
computer architecture; computer interfaces; discrete event simulation; multiprocessing systems; performance evaluation; Network II.5; PAWS; discrete event simulation model; multiprocessor bus architecture; tightly coupled multiprocessor system; workload characterization; Computational modeling; Computer architecture; Computer networks; Discrete event simulation; Microcomputers; Multiprocessing systems; NASA; Performance analysis; Plasma welding; Space shuttles;
Conference_Titel :
Simulation Symposium, 1991., Proceedings of the 24th Annual
Conference_Location :
New Orleans, LA
Print_ISBN :
0-8186-2169-9
DOI :
10.1109/SIMSYM.1991.151489
