Impact of sub-melt laser annealing on Si1-xGex source /drain defectivity

The interaction between sub-melt laser annealing and an embedded Si_1-xGe_x source/drain (S/D) module has been studied in more detail by means of a PFET transistor evaluation and blanket layer characterization. If the integration of the Si_1-xGe_x source/drain and laser anneal modules is not optimized, defects are introduced into the Si substrate as a result of the additional thermal stress. The presence of these defects leads predominantly to a strongly enhanced junction leakage but does not seem to affect the l_on performance. The defect density can be influenced by different process parameters such as laser peak temperature, dwell time, Ge concentration and Si_1-xGe_x thickness. It has been shown that shorter dwell times, lower Ge concentrations and a reduced thickness enable higher laser peak temperatures.