Modeling and simulation of an i860-based multiprocessor

This paper presents the modeling and simulation of a multiprocessor architecture. The methodology included cycle-by-cycle uniprocessor simulation, trace driven multiprocessor simulation, and high-level simulation in an architecture design and assessment system (ADAS). The multiprocessor was designed for digital signal processing (DSP) and used single-chip Intel i860 processors with a shared global memory. The ADAS simulations were found to be most useful for initial simulations, scheduling, and feasibility assessment. The trace driven simulations were found to be very useful for predicting exact performance and for evaluating changes to the DSP algorithms