DocumentCode :
2121867
Title :
FPGA implementation of variants of min-sum algorithm
Author :
Tolouei, Sina ; Banihashemi, Amir H.
Author_Institution :
Dept. of Syst. & Comput. Eng., Carleton Univ., Ottawa, ON
fYear :
2008
fDate :
24-26 June 2008
Firstpage :
80
Lastpage :
83
Abstract :
This paper presents the FPGA implementation of a number of popular decoding algorithms for a regular rate-1/2 low density parity check code with block length 504 bits. The so-called min-sum (MS) algorithm and two of its variants, known as MS with successive relaxation (SR-MS) and MS with unconditional correction (MS-UC), are implemented. We implement the algorithms on a Xilinx XC2VP100 FPGA device with 4-bit quantization. We show that for MS-UC, the circuit utilization increases by about 2% compared to standard MS and that the throughput is the same as that of MS. For SR-MS, the device utilization is increased by about 26% and the throughput is decreased by approximately 20% compared to standard MS. While the throughput and the area and power consumption of our implementation is comparable to the most recent FPGA implementations of LDPC decoders, ours is the first attempt at implementing an iterative decoding algorithm with memory (SR-MS).
Keywords :
field programmable gate arrays; iterative decoding; parity check codes; 4-bit quantization; FPGA implementation; Xilinx XC2VP100 FPGA device; block length; circuit utilization; decoding algorithms; iterative decoding algorithm; min-sum algorithm; regular rate-1/2 low density parity check code; successive relaxation; AWGN; Clocks; Energy consumption; Field programmable gate arrays; Frequency; Iterative algorithms; Iterative decoding; Parity check codes; Quantization; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, 2008 24th Biennial Symposium on
Conference_Location :
Kingston, ON
Print_ISBN :
978-1-4244-1945-6
Electronic_ISBN :
978-1-4244-1946-3
Type :
conf
DOI :
10.1109/BSC.2008.4563210
Filename :
4563210
Link To Document :
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