• DocumentCode
    21222
  • Title

    Graph-Pair Decision Diagram Construction for Topological Symbolic Circuit Analysis

  • Author

    Guoyong Shi

  • Author_Institution
    Sch. of Microelectron., Shanghai Jiao Tong Univ., Shanghai, China
  • Volume
    32
  • Issue
    2
  • fYear
    2013
  • fDate
    Feb. 2013
  • Firstpage
    275
  • Lastpage
    288
  • Abstract
    Symbolic circuit analysis is concerned with analytical construction of circuit response in the frequency (or time) domain, for which an efficient data structure is required. Recent research has justified that the binary decision diagram (BDD) is a superior data structure with the following distinguishing feature: a large number of product terms can be compactly represented by a BDD, on which numerical computations and analytical deductions can be performed directly. Using BDD for symbolic circuit analysis requires an efficient method for construction. In this paper, a graph-based construction method, called graph-pair decision diagram (GPDD), is developed. Given a small-signal circuit, a pair of graphs representing the circuit is created, from which a GPDD is constructed by successively reducing the graph pair. The GPDD algorithm, which generates cancellation-free symbolic terms, differs from the existing determinant decision diagram (DDD) algorithm. Detailed theory and implementable algorithms for the GPDD construction are developed, and a runtime performance comparison to DDD is made. It is demonstrated that the runtime performance using GPDD is comparable to that of DDD in terms of time and memory complexity for exact symbolic analysis, although the GPDD algorithm has to generate a much larger number of symbolic product terms.
  • Keywords
    frequency-domain analysis; graph theory; network analysis; numerical analysis; BDD; DDD algorithm; GPDD; binary decision diagram; cancellation-free symbolic terms; determinant decision diagram algorithm; frequency domain; graph-pair decision diagram construction; memory complexity; numerical computations; small-signal circuit; superior data structure; time complexity; topological symbolic circuit analysis; Algorithm design and analysis; Boolean functions; Circuit analysis; Data structures; Integrated circuit modeling; SPICE; Voltage control; Analog design automation; binary decision diagram (BDD); determinant decision diagram (DDD); graph-pair decision diagram (GPDD); implicit enumeration; symbolic analysis;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2012.2217963
  • Filename
    6416104