DocumentCode :
2122950
Title :
Implementation of DTTB LDPC encoder based on FPGA
Author :
Wen, Zhou ; Yu-huang, Ye ; Kai-Xiong, Su
Author_Institution :
College of Physics and Information Engineering of Fuzhou University, 350002, China
fYear :
2010
fDate :
4-6 Dec. 2010
Firstpage :
2126
Lastpage :
2128
Abstract :
QC-LDPC code is used as the inner channel code in DTTB. In this paper, FPGA implementation of QC-LDPC code based on SRAA is introduced according to the features of QC-LDPC generator matrix. At the same time, the results are verified in the Altera Stratix device.
Keywords :
Clocks; Encoding; Field programmable gate arrays; Generators; Matrix decomposition; Parity check codes; Polynomials; DTTB; FPGA; LDPC;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Information Science and Engineering (ICISE), 2010 2nd International Conference on
Conference_Location :
Hangzhou, China
Print_ISBN :
978-1-4244-7616-9
Type :
conf
DOI :
10.1109/ICISE.2010.5690219
Filename :
5690219
Link To Document :
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